Main Responsibilities and Required Skills for a SMTS Silicon Design Engineer
A SMTS Silicon Design Engineer is a professional who plays a pivotal role in the development and implementation of cutting-edge silicon designs for advanced semiconductor products. These engineers are instrumental in translating design concepts into tangible silicon solutions, pushing the boundaries of technology innovation. In this blog post, we delve into the primary responsibilities and the most in-demand hard and soft skills for SMTS Silicon Design Engineers.
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Main Responsibilities of a SMTS Silicon Design Engineer
The following list describes the typical responsibilities of a SMTS Silicon Design Engineer:
Achieve
Achieve high frequency / low power design.
Address
Address customer requirements and feedback in design iterations.
Analyze
Analyze and address manufacturing-related challenges.
Analyze gating efficiency report to improve RTL quality.
Analyze sophisticated digital design problems and propose solutions.
Analyze the performance issue in architecture and give solution.
Analyze workload in real game and write performance test for game performance evaluation.
Bridge
Bridge the gaps between the Design Team and Performance Verification Team.
Build
Build a large data base for performance / function data.
Build C / C++ model for simulation.
Build microarchitecture specifications.
Build SOC testbech and infra.
Coach
Coach and mentors junior staff.
Collaborate with
Collaborate with architecture and design teams on client roadmap features.
Collaborate with cross-functional teams to define design requirements.
Collaborate with EDA vendors for tool trainings, evaluation and deployment.
Collaborate with foundries and fabrication partners on process technology.
Collaborate with Perf team to develop performance / power model and testing vectors.
Collaborate with Physical design team for timing closure and area / power optimization.
Collaborate with physical design teams for layout implementation.
Collaborate with software teams for system-level integration.
Collaborate with verification team to achieve good coverage.
Communicate
Communicate progress and technical updates to stakeholders.
Compare
Compare our chips with the competitors.
Compose
Compose test plan and validation vectors to ensure functional completeness.
Conduct
Conduct feasibility studies and performance analysis for proposed designs.
Conduct pre-silicon and post-silicon validation testing.
Conduct timing analysis and optimization for design closure.
Contribute
Contribute towards design of hardware irritators to validate features on silicon.
Correlate
Correlate performance data among modeling, pre-silicon and post-silicon.
Co-work with
Co-work with arch / block / SW / perf team for solid plan review and issue discussions.
Co-work with Front End and PD for synthesis optimization and smooth timing signoff.
Create
Create and collect cover-points to drive functional coverage closure.
Create and execute Cache Sub-System test plan.
Debug
Debug and support IP level end2end test, and support FPGA debug.
Debug and support IP level verification, testplan.
Debug and troubleshoot design issues throughout the development cycle.
Debug functional and performance bugs, pre-Si and post-Si.
Debug function and performance bugs of graphics IP.
Debug function and performance issue in RTL simulation & Hardware Emulation & C Model emulation.
Debug function / performance bug of synthetic tests and real game tests.
Debug function / performance bugs of GMHUB IP.
Debug HW emu for low performance.
Debug low power related function bugs of graphics IP.
Debug on Cmodel, RTL and HWEMUL.
Define
Define SoC level feature requirements, and serve as key contact point for chip capabilities.
Design
Design AMD Graphic reference boards and production boards.
Design and implement complex digital and analog circuits.
Design and implement new features in existing tools as well as create entirely new tools.
Design and implement other DFX (debug, characterization, yield etc) logics.
Design and integrate intellectual property (IP) blocks into silicon designs.
Design new architecture to improve performance.
Develop
Develop / analyze power modeling and simulation.
Develop and execute verification plans for functional validation.
Develop and maintain the graphics library for design verification.
Develop architectural specifications for silicon designs.
Develop C++ model for simulation and image quality check.
Develop complex new features for the functional texture block under development.
Develop emulation infrastructure components (i.e. transactors, debug monitors, etc...).
Develop formal verification test plans.
Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
Develop high-performance functional models for AMD SoCs and platform.
Develop / Maintain kinds of graphics libraries for design verification.
Develop micro-architecture for GPU blocks based on architectural requirement.
Develop micro-architecture for GPU blocks based on architecture requirement.
Develop more advanced GPU technology.
Develop reference models for the functionality, performance, and power behavior of the design.
Develop RTL codes for GPU blocks in Verilog HDL.
Develop SOC level design for dGPU product and make functional correct.
Develop test plans and tests' functionality of the models.
Develop, track, and communicate project plans internally and with SCBU customers.
Develop UVM test bench on both block level and IP level for test.
Develop Verilog RTL and Bus Functional Models.
Document
Document the technical design.
Drive
Drive / develop ASIC design flows and scripts.
Drive innovation and continuous improvement in design processes.
Drive innovation to optimize the designs.
Drive technical and resource tradeoffs between parties to achieve goals.
Drive to learn and perform at his or her highest potential in a technical capacity.
Enable
Enable pre-silicon development of firmware, system, driver and application software.
Enhance
Enhance our simulation infrastructure and develop innovative, new debug features.
Ensure
Ensure adherence to quality and reliability standards.
Ensure compliance with industry standards and design methodologies.
Establish
Establish and maintain AMD's technological leadership position in an area.
Evaluate
Evaluate and incorporate new design methodologies and tools.
Evaluate the chip performance of real game in RTL.
Execute
Execute a project independently with global teams to achieve pre-defined goals in time.
Fix
Fix all identified failures in the verification model.
Focus
Focus on timing, LINT and CDC closure to ensure high quality RTL.
Generate
Generate and review design documentation for completeness and accuracy.
Generate and verify DFT structural patterns and functional patterns.
Generate DFT related timing constraints and work with PD team for timing closure.
Generate power feature definition and specifications.
Guide
Guide and mentor junior engineers as required.
Help
Help debug cases and check coverage.
Help PD on the floorplanning and close timing.
Identify
Identify performance issue of GPU, analyze root cause and propose solutions.
Implement
Implement directed and random test cases in C++ / SV / UVM, as well as checkers and assertions.
Implement power optimization techniques in silicon designs.
Implement security features and protocols in silicon designs.
Implement the design in Verilog or System Verilog, ensuring adherence to our RTL coding guidelines.
Improve
Improve and upgrade the Verification environment architecture.
Improve customer satisfaction and image quality.
Improve existing test bench to achieve the goals of reusability, configurability, and scalability.
Improve existing UVM test bench with advanced design verification methodology.
Improve functionality, stability, and performance of existing models.
Initiate
Initiate and Lead Research on GPU architect.
Interface with
Interface with cross-functional teams like RTL, Verification and Physical Design.
Interface with global architecture and design teams, understand graphics SoC design and feature set.
Know
Know backend process of synthesis, DFT, and timing closure.
Lead
Lead a team to work on 30-60 tiles.
Lead Game Bottleneck Based Performance Verification, Evaluation and Analysis for new chip.
Lead Performance Verification and Analysis for new chip.
Learn
Learn new features, write test plan and new tests for new graphics chips.
Learn the spec and implement in RTL.
Leverage
Leverage formal verification convergency techniques to drive verification closure.
Maintain
Maintain and Interface with existing random generators, models and APIs.
Make
Make sure AMD next generation GFXIP can meet performance / power / function expectation.
Make sure AMD next generation SOC can meet performance / power / function expectation.
Make technical decisions.
Manage
Manage project schedules and milestones.
Mentor
Mentor junior engineers and provide technical guidance.
Mentor Junior engineers to complete their ideas and tasks.
Optimize
Optimize chip setting for better performance.
Optimize logic for performance, power, and area.
Optimize performance and area utilization in silicon designs.
Participate
Participate in design reviews and provide technical insights.
Participate in SOC full Chip DFT feature and architecture definition.
Participate in various DV methodologies and flows development including VC-formal, HLS, UVM-SystemC.
Perform
Perform RTL coding and synthesis for digital circuits.
Plan
Plan and implement the UVM testbench, functional coverage model and assertions.
Plan / Implement block / chip level DFT RTL designs basing on FloorPlan.
Provide
Provide and drive the platform solution by leading the related design teams.
Provide consultative direction with management.
Provide expertise in design, process and integration for advanced technology development.
Provide expertise in GPU benchmark & game technology.
Provide technical guidance and innovative ideas to improve quality, processes and productivity.
Provide technical leadership, guidance, and mentorship to junior Physical Design Engineers.
Provide technical leadership to game / benchmark algorithm analysis.
Provide technical support to other teams.
Provide technical support to other teams, including performance and power.
Provide the technical guidance to customer support team.
Provide the technical leadership to the DV team for the new Southbridge project.
Recommend
Recommend improvements, optimization and power saving enhancements.
Represent
Represent AMD to the outside technical community, partners and vendors.
Research
Research on image processing algorithm with CMOS camera input.
Resolve
Resolve formality, leda, CDC, connectivity and repeater issue.
Review
Review architecture spec and identify key designs / features suitable for new methodology.
Review architecture specifications.
Review verification plans to ensure design coverage.
Run
Run front-end integration flow (synthesis, LINT, DFT, etc.) , deliver netlists with good quality.
Scan
Scan / ATPG, knowledge of industry standard DFT features, simulation debug, MBIST.
Scan Synthesis, Scan re-order.
Simulate
Simulate new architecture and algorithms.
Solve
Solve complex, novel and non-recurring problems.
Stay updated on
Stay updated on industry trends and emerging technologies.
Study
Study new architecture, write test plan and performance tests for new graphics chips.
Support
Support emulation acceleration, performance, and power modeling.
Support emulation program execution with debug on hardware emulator models.
Support integration and qualification of SOC integration.
Support internal and external teams to correctly use the library.
Support post-silicon characterization, debug and productization.
Support silicon bring-up and diagnostics.
Take
Take part in host controller design, based on architectural requirement for next generation IO.
Understand
Understand logical design architecture and provide the analyzed data to architects for review.
Understand the architecture of the GMHUB IP and functional block being designed.
Understand the architecture of the GPU and functional block being designed.
Understand the architecture of the graphics IP and functional block being developed.
Use
Use efficient automation while improving the productivity.
User
User interface development in Visual Studio.
Utilize
Utilize industry-standard CAD tools for design and simulation.
Validate
Validate and qualify the design through simulation, formal verification and Lab equipment.
Verify
Verify AMD's next-generation IP subsystem of computer, graphics, and visualization SoCs.
Verify design functionality through simulation and emulation.
Verify the performance model to guarantee that the prediction is accurate in silicon and RTL model.
Work with
Work closely with Architecture and Design teams to understand relevant features the basic design.
Work closely with architecture teams to understand and model new designs.
Work closely with block architect to understand design trade-offs and performance challenges.
Work closely with DV team to analyze and debug failures.
Work closely with firmware team for firmware developments.
Work closely with IP and system architects to micro-architect cutting edge features.
Work closely with Marketing to define the board spec.
Work closely with Silicon team for the product definition.
Work closely with SOC Architecture team for SOC clocks statistical timing target goals.
Work closely with software / FW team for further developments.
Work independently on various DV tasks and providing technical guidance to the DV team.
Work independently with limited supervision, strong sense of work planning and on-time delivery.
Work on CIT IP and subsystem level verification, focus on Power and Performance verification.
Work on GCDV / PV / HWEMU / DFP verification tasks.
Work on low power verification tasks including Clock Gating / Power Gating DV.
Work with architects and designers to debug functional and performance issues.
Work with architecture / IP designers to get a full deep insight on the design under test.
Work with both analog engineers to model critical aspects of PHY.
Work with DV folks to define, analyze and debug various functional, performance and power features.
Work with Front end / package / CAD / Architecture / DFX team of related PD topics.
Work with gfxip verification team and arch / designer to understand design and features.
Work with global teams (Algorithm, design, firmware, software, tuning, SOC, DFT.).
Work with Physical Design folks to resolve timing violations and determine best floorplan layout.
Work with Physical Design team to ensure accurate implementation of the design.
Work with RTL designers and algorithm teams to close all possible issues during implementation.
Work with RTL designers to create formal verification friendly reference models.
Work with RTL owner and physical design team on timing closure and report check.
Work with RTL, Verification engineers to ensure proper implementation of algorithms.Work with SW / HW team to analyze the performance.
Work with Synthesis and PD teams and improve frequency and power.
Work with the most talent people in computer graphics.
Work with verification engineer on debugging.
Work with Verification team and contribute to test plans for high quality IP / block.
Write
Write and refine Silicon Verification testplans collaborating with RTL, DV engineers.
Write assertions and coverage properties to aid in DV closure.
Write custom tools and scripts to integrate point tools into a highly optimized workflow.
Write SOC level architecture specifications and other documentation in a clear and concise fashion.
Write tests and debug functional, performance, and power related issues.
Most In-demand Hard Skills
The following list describes the most required technical skills of a SMTS Silicon Design Engineer:
Proficiency in Verilog and VHDL hardware description languages.
Expertise in digital and analog circuit design principles.
Knowledge of ASIC and FPGA design methodologies.
Experience with EDA tools such as Cadence and Synopsys.
Familiarity with RTL synthesis and place-and-route techniques.
Understanding of clock domain crossing (CDC) and asynchronous design issues.
Skill in low-power design techniques and methodologies.
Proficiency in scripting languages such as Perl and Python for automation.
Experience with simulation tools like ModelSim and VCS.
Knowledge of formal verification techniques and tools.
Familiarity with industry-standard bus protocols (e.g., AXI, PCIe).
Understanding of signal integrity and timing closure concepts.
Experience with mixed-signal design and verification.
Knowledge of memory architectures and interfaces.
Proficiency in hardware security concepts and protocols.
Understanding of DFT (Design for Testability) principles.
Experience with silicon validation and characterization.
Skill in system-level modeling and simulation.
Familiarity with semiconductor fabrication processes.
Knowledge of industry standards such as ISO 26262 and ASIL.
Most In-demand Soft Skills
The following list describes the most required soft skills of a SMTS Silicon Design Engineer:
Effective communication skills for collaboration and documentation.
Teamwork and collaboration across diverse engineering teams.
Problem-solving and analytical thinking in complex design scenarios.
Adaptability to changing project requirements and priorities.
Time management and organization to meet project deadlines.
Attention to detail in design documentation and verification plans.
Leadership and initiative in driving design projects forward.
Adaptability and resilience in navigating design challenges.
Conflict resolution and negotiation skills in cross-functional teams.
Continuous learning mindset to stay abreast of technology trends.
Conclusion
In the realm of semiconductor design, SMTS Silicon Design Engineers are at the forefront of innovation, shaping the future of technology with their expertise and ingenuity. Through a combination of technical prowess and soft skills, they drive the development of next-generation silicon solutions, fueling progress and transformation in the digital landscape.
