Main Responsibilities and Required Skills for Design Verification Engineer
A Design Verification Engineer (DVE) is a prefessional who is responsible for verifying that the design of a product or system meets its intended functionality and performance requirements. They develop test plans and test cases to identify potential design issues and provide recommendations for improvements. In this blog post we describe the primary responsibilities and the most in-demand hard and soft skills for Design Verification Engineers.
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Main Responsibilities of Design Verification Engineer
The following list describes the typical responsibilities of a Design Verification Engineer:
Analyze
Analyze equipment to establish operation data, conduct experimental tests, and evaluate results.
Analyze functional / code coverage result and identify the coverage holes.
Architect
Architect testbench with maximum reusability in mind, and create UVM libraries.
Assist
Assist IP to release its codes to SOC and resolve interdepencies with other IP and SOC codes.
Assume
Assume technical leadership and hands on development tasks.
Attend
Attend verification reviews and set standard for coding quality.
Automate
Automate and improve test suite efficiency.
Build
Build a test bench and monitors for DUT.
Build block / subsystem / chip level testbench using best in class DV methodology.
Build C / C++ / UVM model for simulation.
Build, reuse and debug test cases and test bench components for IP and SOC consumption.
Build SystemVerilog and / or C / C++ models and test sequence libraries for simulation.
Build test bench, agents, monitors and scoreboard for DUV.
Build test bench and monitors for DUT.
Build test-benches from scratch.
Build up test lib and testbench.
Coach
Coach and mentors experienced staff.
Collaborate with
Collaborate with architects and TG / PG RTL / Designers.
Collaborate with architects, designers, and pre and post silicon verification teams.
Collaborate with architects / designers to understand design features.
Collaborate with architects to understand block design.
Communicate
Communicate openly and clearly in meetings, presentations, emails, and reports.
Compose
Compose test and coverage plan, and validation vectors to ensure functional completeness.
Concept
Concept and flow of design verification.
Construct
Construct block level test bench in UVM.
Contribute to
Contribute towards design of hardware irritators to validate features on silicon.
Contribute towards FPGA Verification at block and system levels, lab bring-up and validation.
Cooperate
Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity.
Coordinate
Coordinate work with third party test houses as required.
Create
Create / Implement Verification Test plans that are detailed and well thought out.
Create, reuse and debug test cases and test bench components for IP and SOC consumption.
Create, reuse and debug test cases and test bench components for IP development.
Create SoC test plan related to the IP features, run simulations and regressions.
Create Test plans and other documents.
Debug
Debug failures in simulation and collaborate with designers in identifying root-cause issues.
Debug failures, manage bug tracking, and close coverage.
Debug function / performance bugs of Display IP in Emulation and Simulation Environments.
Debug function / performance bugs of graphics, APU and server chips.
Debug test faliures and correct test and testbench related failures.
Debug triage of failures from simulation and emulation environment for CORE or sub-level regressions.
Define
Define and track detailed test plans for the different modules and top level systems.
Define module interfaces / formats for simulation.
Deploy
Deploy solutions with focus on improving company efficiency and design quality.
Deploy the advanced verification methodology and infrastructure of the SOC / IP.
Design
Design and execute test plans for these KPIs.
Design and implement models and testbenches in UVM, systemC and C / C++.
Design and implement test benches in Verilog, C / C++, or UVM.
Design / Design Verification Engineer for IP Deployment.
Design system test procedures.
Design Verification and digital design experience.
Design Verification Engineer GFXIP Mobile, Senior Member of Technical Staff.
Determine
Determine architecture design, logic design, and system simulation.
Develop
Develop, adapt, and verify IP performance tests.
Develop and execute on verification test plans in emulation environments.
Develop and execute pre-silicon verification test plans.
Develop and implement SystemVerilog UVM constrained random test sequences and C-based directed tests.
Develop and maintain test benches.
Develop and review block and chip level verification environments and test plans.
Develop design verification testbenches using UVM and maintain them.
Develop infrastructure and environment for IP / SoC level design verification.
Develop or adapt, and verify IP performance tests, metrics.
Develop or adapt test libraries, emulation model, and test cases from existing IP.
Develop or adapt tests cases, test libraries from DCN IP or SOC environment.
Develop quality, timely and cost-effective solutions independently.
Develop risk-based and statistically significant sampling plans for technical requirements.
Develop, simulate and debug directed and random stimulus and assembly level tests.
Develop System Verilog, C-model, and C++ bus functional models for specific features.
Develop System Verilog / UVM testbenches for the functional verification and HW / SW Co-verification.
Develop test and coverage plans to ensure the functional, performance and power completeness.
Develop testbench components including stimulus drivers, monitors and checkers.
Develop test plans and implement them (in C++) for several unit level blocks.
Develop test plans and write directed / constrained-random verification tests.
Develop tests or methods to guarantee design quality and completeness.
Develop tools, infrastructure, processes and flows to enable functional verification.
Develop verification components and tools.
Develop verification plans for all features under your care.
Develop Verilog, C-model, and C++ bus functional models for specific features.
Document
Document testplans and testbench component plans and drive reviews with peers and partners.
Draft
Draft block level test plan and functional coverage specification.
Drive
Drive full chip verification using VIPs eg. PCIE, DDR.
Drive new improvements and initiatives across the broader team.
Execute
Execute and review tests to meet functional and code coverage requirements.
Execute and schedule regression runs, reporting regression results.
Execute a project independently with global teams to achieve pre-defined goals in time.
Find
Find bugs in the design and work with RTL writers to resolve all failures and discrepancies.
Follow
Follow the process and good practices to develop UVC and testbench for design verification.
Generate
Generate directed and constrained random tests.
Grow
Grow verification infrastructure.
Help
Help scoping out the testbench architecture and the simulation configuration.
Help to improve DV environment building flow.
Identify
Identify and address areas of concern to meet design quality objectives.
Implement
Implement directed and random test cases and TB in C++ / UVM, as well as checkers and assertions.
Implement testbench and scoreboards / checkers.
Implement test plans, verification plans, testbenches and test cases and participate in test debug.
Implement test sequences as per plan and debug failures.
Improve
Improve existing UVM test bench with advanced design verification methodology.
Initiate
Initiate test plan review and verification reviews with the teams at every stage.
Interact with
Interact with Vendors on tool-related issues and provide guidance for tool improvements.
Keep
Keep track of coverage metrics and bugs encountered and fixed.
Lead
Lead major initiatives / projects.
Lead multiple projects and mentor junior engineers.
Lead the effort to integrate NBIO subsystem to SoC and provide support to SoC team.
Leverage
Leverage or adapt test libraries, emulation models, and test cases from existing IP.
Leverage your understanding on building randomly constrained verification simulation test-benches.
Maintain
Maintain and improve emulation infrastructure and methodology.
Maintain current knowledge in latest testing methodologies.
Maintain regression suites and flow infrastructure.
Manage
Manage and coach team on ASIC verification tasks.
Mentor
Mentor junior engineers so they can mature into strong contributors.
Oversee
Oversee definition, design, verification, and documentation for ASIC development.
Participate
Participate and contribute to test automation objectives and initiatives.
Participate in development of formal verification techniques.
Participate in IP / Company's methodology improvement, and new technology / architecture definition.
Participate in selecting best in class 3rd party protocol verification IP.
Participate in technical reviews of the specifications, design and test plans.
Participate in the bring-up and debug of the device prototype.
Participate in verification of complex IP blocks.
Perform
Perform project definition, training, and documentation.
Provide
Provide executive level readouts and status reports to all levels of management within AMD.
Provide technical guidance and innovative ideas to improve quality, processes and productivity.
Provide technical guidance to team.
Provide technical support to other teams.
Provide the documentation and implementation for test benches, DV models, and test cases.
Provide the technical leadership to the DV team for the new Southbridge project.
Read
Read IAS and design specs to understand the design requirement and build corresponding testplan.
Report
Report results to cross-functional teams and work with design teams to improve product performance.
Represent
Represent the company at industry forum and conferences.
Resolve
Resolve pre-layout and post-layout timing issues and aiding in ECO implementation as applicable.
Review
Review formal setups and proofs with design and verification teams.
Review, improve tests to verify bug fixes.
Review metrics and deliver task with high quality.
Review the testplan with arch / design engineers.
Scope
Scope requirements and resources to meet fast paced project schedules.
Set
Set direction for high-impact and / or long-range strategic / technical projects.
Suggest
Suggest details improvements to existing TB components / processes and implement them.
Support
Support customers on the IP usage and programming.
Support efforts to reproduce silicon failures on pre-silicon and FPGA / Emulation platforms.
Support integration and qualification of all the IPs for SoC.
Support system bring up and debug activities.
Take
Take dedicated ownership to execute block level verification.
Test
Test plan and execute test plan for various features.
Triage
Triage failures and provide support to design engineers to isolate the problems.
Triage failures in regression and help designer root cause the bug.
Understand
Understand dependencies, and identify bottlenecks and risks early.
Understand industry standard display I / O specifications.
Understand logical design architecture and provide the analyzed data to architects for review.
Understand the architecture and designs being delivered to direct the DV team optimally.
Understand the architecture of the Display IP and functional block being designed.
Understand the ASIC design / verification flow to accomplish targets.
Understand the functional and performance requirements of the Display IP within an APU and dGPU SOC.
Use
Use advanced verification methodologies for the verification of sophisticated designs.
Use Defect Tracking System to report and / or resolve product issues.
Use test equipment to collect data on device interop and compliance to improve AMD products.
Validate
Validate first silicon designs and ensure it is incorporated into our hardware products.
Verify
Verify sophisticated design blocks using equally complex SV / UVM verification environments.
Verify Square's custom ASICs to make sure it meets our security and payment requirements.
Verify the functionality and verify conformance to the ISA.
Work with
Work closely with designers, micro architects & f / w to resolve issues.
Work closely with SOC team to ensure IP delivery meets with requirements.
Work on engineering and research assignments with F500 companies and startups.
Work on RTL Design implementation, LINT / CDC, Synthesis and Timing closure.
Work on test plans, TB development, test case development, regression and coverage closure.
Work on the USB4 IP verification.
Work with all partners such as lead architects to understand features to be implemented and verified.
Work with design engineer to improve the coverage score.
Work with designer to transition any unit-level work from design to verification.
Work with DV architect to define and develop new verification frameworks and test library.
Work with existing tools / flows or develop new tools / flows to facilitate in power analysis.
Work with Graphics IP arch / designer to verify performance and reveal performance holes.
Work with Graphics IP verification team / arch / designer to understand design and new features.
Work with HW, diagnostics and SW engineers to create programming sequences for lab characterization.
Work with internal fabrication and prototyping teams to build test equipment in our labs.
Work with IP verification team / arch / designer to understand design and new features.
Work with North America leadership on strategies to expand scope.
Work with RTL designer on DUT verification.
Work with RTL writers to resolve all simulation failures and discrepancies.
Work with senior engineer to scopes out the testbench architecture.
Work with SOC and IP design team to debug test failures at IP and chip level.
Work with SOC teams to debug test environment issues and failing test cases.
Work with the systems and software teams on emulation platforms.
Write
Write and augment existing testplans.
Most In-demand Hard Skills
The following list describes the most required technical skills of a Design Verification Engineer:
Computer Engineering
Computer Architecture
OVM
Scripting Languages
Unix
Systemverilog
EE
Debug Tools
Functional Coverage
Simulation
CS
CE
Linux Environment
Assertions
Scripting
VMM
TCL
Most In-demand Soft Skills
The following list describes the most required soft skills of a Design Verification Engineer:
Written and oral communication skills
Analytical ability
Problem-solving attitude
Attention to detail
Interpersonal skills
Organized
Self-motivated
Self-starter
Team player
Independently drive tasks to completion
Teamwork
Continuous improvement
Detail oriented people
Innovative
Leadership
Methodical
